iPort/AFM I2C Clock Rate FAQ (Frequently Asked Questions)

What controls the iPort/AFM I2C clock rate?

The I2C clock rate is controlled by many factors. In the iPort/AFM case, the master clock rate is controlled by:

1. Adapter crystal frequency
This is controlled by RS-232 baud rate requirements. This is about 11/12ths of the maximum bus clock frequency.

2. Interrupt latency
Time required for our microcontroller to service non-i2c devices. This occurs between bytes for standard commands, and between bits for eXtended commands.

3. Inter-byte data processing
This is overhead time it takes to load the next byte in a message. It occurs between the acknowledge bit of one byte, and the 1st bit of the following byte.

4. Data source (internal buffers or host computer link)
We can send up to 256 bytes from our internal buffer. After that is exhausted, we rely on the host computer link to send additional data. The data is sent out on the bus as soon as it is received.

5. Host link baud rate.
eXtended commands use firmware "bit-banging", and are executed when received from the host computer, although some commands can be slowed by a clock-stretch from a slave device.

6. Slave clock stretching.
All standard, and most eXtended commands can be slowed by a clock-stretching slave device.

7. Clock implementation
Hardware (standard commands) or firmware (eXtended commands).

I2C clocking is very dynamic. It can change bit to bit, byte to byte. The I2C specification does not require a fixed rate, only a maximum rate.

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